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SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions.
TM
memory
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50312-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
64M (x16) FLASH MEMORY & 16M (x16) Mobile FCRAMTM
MB84VD23381HJ-70
s FEATURES
* Power Supply Voltage of 2.7 V to 3.1 V * High Performance 70 ns maximum random access time (Flash) 60 ns maximum random access time (FCRAM) * Operating Temperature -30 C to +85 C * Package 56-ball BGA
(Continued)
s PRODUCT LINEUP
Flash Supply Voltage (V) Max Random Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 3.0 V 70 70 30
+0.1 V -0.3 V
FCRAM VCCr* = 3.0 V 60 60 35
+0.1 V -0.3 V
* : Both VCCf and VCCr must be the same level when either part is being accessed.
s PACKAGE
56-ball plastic FBGA
BGA-56P-M04
MBVD23381HJ-70
(Continued)
-- FLASH MEMORY * Simultaneous Read/Write operations (Dual Bank) * FlexBankTM*1 Bank A : 8 Mbit (8 KB x 8 and 64 KB x 15) Bank B : 24 Mbit (64 KB x 48) Bank C : 24 Mbit (64 KB x 48) Bank D : 8 Mbit (8 KB x 8 and 64 KB x 15) Two virtual Banks are chosen from the combination of four physical banks. Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program * Minimum 100,000 program/erase cycles * Sector erase architecture Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word. Any combination of sectors can be concurrently erased. It also supports full chip erase. * WP/ACC input pin At VIL, allows protection of "outermost" 2 x 8 Kbytes on both ends of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance * Embedded EraseTM*2 Algorithms Automatically preprograms and erases the chip or any sector * Embedded ProgramTM*2 Algorithms Automatically writes and verifies data at specified address * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, the device automatically switches itself to low power mode. * Low VCCf write inhibit 2.5 V * Program Suspend/Resume Suspends the program operation to allow a read in another byte * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Please refer to "MBM29DL64DH" Datasheet in deteiled function (Continued)
2
MB84VD23381HJ-70
(Continued)
-- FCRAMTM*3 * Power Dissipation Operating : 20 mA Max Standby : 70 A Max * Power Down Mode Sleep : 10 A Max * Power Down Control by CE2r * Byte Write Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8) * 8 words Address Access Capability
*1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3: FCRAMTM is a trademark of Fujitsu Limited, Japan.
3
MBVD23381HJ-70
s PIN ASSIGNMENT
(Top View) Marking Side
B8 A15 A7 A11 A6 A8 A5 WE A4 B7 A12 B6 A19 B5 CE2r B4
C8 A21 C7 A13 C6 A9 C5 A20 C4 RY/BY C3 A18 C2 A5 C1 A2
D8 N.C. D7 A14 D6 A10
E8 A16 E7 N.C. E6 DQ6
F8 N.C. F7 DQ15 F6 DQ13 F5 DQ4 F4 DQ3
G8 Vss G7 DQ7 G6 DQ12 G5 Vccr G4 Vccf G3 DQ10 G2 DQ0 G1 CE1r H7 DQ14 H6 DQ5 H5 N.C. H4 DQ11 H3 DQ2 H2 DQ8
WP/ACC RESET A3 LB A2 A7 B3 UB B2 A6 B1
D3 A17 D2 A4 D1 A1
E3 DQ1 E2 VSS E1 A0
F3 DQ9 F2 OE F1 CEf
INDEX MARK
A3
(BGA-56P-M04)
4
MB84VD23381HJ-70
s PIN DESCRIPTION
Pin name A19 to A0 A21, A20 DQ15 to DQ0 CEf CE1r CE2r OE WE RY/BY UB LB RESET WP/ACC N.C. VSS VCCf VCCr Input/ Output I I I/O I I I I I O I I I I -- Power Power Power Address Inputs (Common) Address Inputs (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Description
5
MBVD23381HJ-70
s BLOCK DIAGRAM
VCCf A21 to A0 A21 to A0 WP/ACC RESET CEf
VSS RY/BY
64 M bit Flash Memory DQ15 to DQ0
DQ15 to DQ0 VCCr A19 to A0 DQ15 to DQ0 LB UB WE OE CE1r CE2r 16 M bit FCRAM VSS
6
MB84VD23381HJ-70
s DEVICE BUS OPERATIONS
Operation*1, *2 Full Standby Output Disable*3 L Read from Flash*4 Write to Flash Read from FCRAM*10 FCRAM No Read L L H H H H H L L H H H H L H L L H L H H X X L*7 H L Write to FCRAM H L H H L H L FCRAM No Write Flash Temporary Sector Group Unprotection*5 Flash Hardware Reset Flash Boot Block Sector Write Protection FCRAM Power Down*6 H X X X X L X H X X H X H X L H X X X X L X X X X H X X X X X X L*7 H L L H H X X X X Valid X X X X Valid Valid Valid Valid Valid DOUT DIN DIN DOUT DIN DIN H H H H X X X X CEf CE1r CE2r OE WE LB UB H H H L H H H X X X*8 High-Z High-Z H X H X X X X A21 to DQ7 to DQ15 to RESET A0 DQ0 DQ8 X High-Z High-Z H WP/ ACC*9 X
High-Z High-Z DIN High-Z DIN DIN DIN High-Z
H
X
High-Z High-Z X X
H VID L X X
X X X L X
High-Z High-Z X X
High-Z High-Z
Legend : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : Do not apply for a following state two or more on the same time; 1) CEf = VIL 2) CE1r = VIL and CE2r = VIH *3 : FCRAM Output Disable mode should not be kept longer than 1 s. *4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5 : It is also used for the extended sector group protections. *6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. *7 : Either or both LB and UB must be Low for Read operation. *8 : Can be either VIL or VIH but must be valid before FCRAM Read or Write. *9 : Protect " outer most " 2 x 8K bytes ( 4 words ) on both ends of the boot block sectors. *10 : FCRAM Byte control at Read mode is not supported.
7
MBVD23381HJ-70
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET ,WP/ACC *1 VCCf/VCCr Supply * RESET *
2 3 1
Symbol Tstg TA VIN, VOUT VCCf,VCCr VIN VIN
Rating Min -55 -30 -0.3 -0.3 -0.5 -0.5 Max +125 +85 VCCf + 0.3 VCCr + 0.3 +3.3 + 13.0 +10.5
Unit C C V V V V V
WP/ACC *
*1: Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCf/VCCr Supply Voltages Symbol TA VCCf, VCCr Value Min -30 +2.7 Max +85 +3.1 Unit C V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
8
MB84VD23381HJ-70
s ELECTRICAL CHARACTERISTICS (DC Characteristics)
Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Flash VCC Active Current (Read) *1 Flash VCC Active Current (Program/Erase) *2 Flash VCC Active Current (Read-While-Program) *5 Flash VCC Active Current (Read-While-Erase) *5 Flash VCC Active Current (Erase-Suspend-Program) WP/ACC Acceleration Program Current Flash VCC Current (Standby) Flash VCC Current (Standby,Reset) Flash VCC Current (Automatic Sleep Mode)*3 Symbol ILI ILO ILIT ICC1f ICC2f ICC3f ICC4f ICC5f IACC Conditions VIN = VSS to VCCf, VCCr VOUT = VSS to VCCf, VCCr, Output Disable VCCf = VCCf Max, RESET = 12.5 V CEf = VIL, OE = VIH tCYCLE =5 MHz tCYCLE =1 MHz Value Min -1.0 -1.0 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- Max +1.0 +1.0 35 18 4 35 53 53 40 20 Unit A A A mA mA mA mA mA mA mA
CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCf = VCCf Max, WP/ACC = VACC Max VCCf = VCCf Max, CEf = VCCf 0.3 V, RESET= VCCf 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCCf Max, RESET= VSS 0.3 V VCCf = VCCf Max, CEf= VSS 0.3 V, RESET= VCCf 0.3 V, VIN = VCCf 0.3 V or VSSf 0.3 V VCCr = VCCr Max, tRC / tWC = Min CE1r = VIL, CE2r = VIH, VIN = VCCr - 0.5 V or VIL, tRC / tWC = 1 s IOUT = 0 mA*7 VCCr = VCCr Max, VIN < 0.2 V or VIN > VCCr - 0.2 V, CE1r > VCCr - 0.2 V, CE2r > VCCr - 0.2 V VCCr = VCCr Max, CE2r < 0.2 V, VIN = VIH or VIL -- --
ISB1f ISB2f ISB3f ICC1r
-- -- -- -- --
1 1 1 -- --
5 5 5 20 3
A A A
FCRAM VCC Active Current*8
ICC2r
mA
FCRAM VCC Standby Current*8
ISB1r
--
--
70
A
FCRAM VCC Power Down Current Input Low Level Input High Level
IDDPSr VIL VIH
-- -0.3 2.2
-- -- --
10 0.5 VCC+ 0.2 *6
A V V
(Continued)
9
MBVD23381HJ-70
(Continued)
Parameter Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration *4 Output Low Voltage Level Output High Voltage Level Flash Low VCCf Lock-Out Voltage Symbol VID Conditions Value Min 11.5 Typ 12 Max 12.5 Unit
--
V
VACC VOLf VOLr VOHf VOHr VLKO
-- VCCf = VCCf Min, IOL= 4.0 mA VCCr = VCCr Min, IOL =1.0 mA VCCf = VCCf Min, IOH=-2.0 mA VCCr = VCCr Min, IOH=-0.5mA -- Flash FCRAM Flash FCRAM
8.5 -- -- 2.4 2.2 2.3
9.0 -- -- -- -- 2.4
9.5 0.45 0.4 -- -- 2.5
V V V V V V
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4 : Applicable for only VCCf applying. *5 : Embedded Alogorithm (program or erase) is in progress (@5 MHz). *6 : VCC indicates lower of VCCf or VCCr. *7 : FCRAM Characteristics are mesured after following POWER-UP timing. *8 : IOUT depends on the output load conditions.
10
MB84VD23381HJ-70
s ELECTRICAL CHARACTERISTICS (AC Characteristics)
* CE Timing Parameter CE Recover Time CE Hold Time CE1r High to WE Invalid time for Standby Entry Symbol JEDEC -- -- -- Standard tCCR tCHOLD tCHWX Condition -- -- -- Value Min 0 3 10 Max -- -- -- Unit ns ns ns
* Timing Diagram for alternating RAM to Flash
CEf
tCCR
tCCR
CE1r
WE
tCHWX tCHOLD
tCCR
tCCR
CE2r
* Flash Characteristics Please refer to "s 64M FLASH MEMORY CHARACTERISTICS FOR MCP". * FCRAM Characteristics Please refer to "s 16M FCRAM CHARACTERISTICS FOR MCP".
11
MBVD23381HJ-70
s 64M FLASH MEMORY CHARACTERISTICS FOR MCP
1. Flexible Sector-erase Architecture on Flash Memory * Sixteen 4K words, and one hundred twenty-six 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability.
Word Mode 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh Word Mode 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h 3FFFFFh
Bank A
Bank B
SA0 : 8KB (4KW) SA1 : 8KB (4KW) SA2 : 8KB (4KW) SA3 : 8KB (4KW) SA4 : 8KB (4KW) SA5 : 8KB (4KW) SA6 : 8KB (4KW) SA7 : 8KB (4KW) SA8 : 64KB (32KW) SA9 : 64KB (32KW) SA10 : 64KB (32KW) SA11 : 64KB (32KW) SA12 : 64KB (32KW) SA13 : 64KB (32KW) SA14 : 64KB (32KW) SA15 : 64KB (32KW) SA16 : 64KB (32KW) SA17 : 64KB (32KW) SA18 : 64KB (32KW) SA19 : 64KB (32KW) SA20 : 64KB (32KW) SA21 : 64KB (32KW) SA22 : 64KB (32KW) SA23 : 64KB (32KW) SA24 : 64KB (32KW) SA25 : 64KB (32KW) SA26 : 64KB (32KW) SA27 : 64KB (32KW) SA28 : 64KB (32KW) SA29 : 64KB (32KW) SA30 : 64KB (32KW) SA31 : 64KB (32KW) SA32 : 64KB (32KW) SA33 : 64KB (32KW) SA34 : 64KB (32KW) SA35 : 64KB (32KW) SA36 : 64KB (32KW) SA37 : 64KB (32KW) SA38 : 64KB (32KW) SA39 : 64KB (32KW) SA40 : 64KB (32KW) SA41 : 64KB (32KW) SA42 : 64KB (32KW) SA43 : 64KB (32KW) SA44 : 64KB (32KW) SA45 : 64KB (32KW) SA46 : 64KB (32KW) SA47 : 64KB (32KW) SA48 : 64KB (32KW) SA49 : 64KB (32KW) SA50 : 64KB (32KW) SA51 : 64KB (32KW) SA52 : 64KB (32KW) SA53 : 64KB (32KW) SA54 : 64KB (32KW) SA55 : 64KB (32KW) SA56 : 64KB (32KW) SA57 : 64KB (32KW) SA58 : 64KB (32KW) SA59 : 64KB (32KW) SA60 : 64KB (32KW) SA61 : 64KB (32KW) SA62 : 64KB (32KW) SA63 : 64KB (32KW) SA64 : 64KB (32KW) SA65 : 64KB (32KW) SA66 : 64KB (32KW) SA67 : 64KB (32KW) SA68 : 64KB (32KW) SA69 : 64KB (32KW) SA70 : 64KB (32KW)
Bank C
Bank D
SA71 : 64KB (32KW) SA72 : 64KB (32KW) SA73 : 64KB (32KW) SA74 : 64KB (32KW) SA75 : 64KB (32KW) SA76 : 64KB (32KW) SA77 : 64KB (32KW) SA78 : 64KB (32KW) SA79 : 64KB (32KW) SA80 : 64KB (32KW) SA81 : 64KB (32KW) SA82 : 64KB (32KW) SA83 : 64KB (32KW) SA84 : 64KB (32KW) SA85 : 64KB (32KW) SA86 : 64KB (32KW) SA87 : 64KB (32KW) SA88 : 64KB (32KW) SA89 : 64KB (32KW) SA90 : 64KB (32KW) SA91 : 64KB (32KW) SA92 : 64KB (32KW) SA93 : 64KB (32KW) SA94 : 64KB (32KW) SA95 : 64KB (32KW) SA96 : 64KB (32KW) SA97 : 64KB (32KW) SA98 : 64KB (32KW) SA99 : 64KB (32KW) SA100 : 64KB (32KW) SA101 : 64KB (32KW) SA102 : 64KB (32KW) SA103 : 64KB (32KW) SA104 : 64KB (32KW) SA105 : 64KB (32KW) SA106 : 64KB (32KW) SA107 : 64KB (32KW) SA108 : 64KB (32KW) SA109 : 64KB (32KW) SA110 : 64KB (32KW) SA111 : 64KB (32KW) SA112 : 64KB (32KW) SA113 : 64KB (32KW) SA114 : 64KB (32KW) SA115 : 64KB (32KW) SA116 : 64KB (32KW) SA117 : 64KB (32KW) SA118 : 64KB (32KW) SA119 : 64KB (32KW) SA120 : 64KB (32KW) SA121 : 64KB (32KW) SA122 : 64KB (32KW) SA123 : 64KB (32KW) SA124 : 64KB (32KW) SA125 : 64KB (32KW) SA126 : 64KB (32KW) SA127 : 64KB (32KW) SA128 : 64KB (32KW) SA129 : 64KB (32KW) SA130 : 64KB (32KW) SA131 : 64KB (32KW) SA132 : 64KB (32KW) SA133 : 64KB (32KW) SA134 : 8KB (4KW) SA135 : 8KB (4KW) SA136 : 8KB (4KW) SA137 : 8KB (4KW) SA138 : 8KB (4KW) SA139 : 8KB (4KW) SA140 : 8KB (4KW) SA141 : 8KB (4KW)
Sector Architecture 12
MB84VD23381HJ-70
FlexBankTM Architecture Bank Splits 1 2 3 4 Bank 1 Volume 8 Mbit 24 Mbit 24 Mbit 8 Mbit Combination Bank A Bank B Bank C Bank D Volume 56 Mbit 40 Mbit 40 Mbit 56 Mbit Bank 2 Combination Remainder (Bank B, C, D) Remainder (Bank A, C, D) Remainder (Bank A, B, D) Remainder (Bank A, B, C)
Example of Virtual Banks Combination Bank 1 Bank Splits Volume Combination Sector Size Bank 2 Volume Combination Sector Size Bank B + 8 x 8 Kbyte/4 Kword 56 Mbit Bank C + + 111 x 64 Kbyte/32 Kword Bank D Bank B 48 Mbit + 96 x 64 Kbyte/32 Kword Bank C Bank A + 16 x 8 Kbyte/4 Kword 40 Mbit Bank C + + 78 x 64 Kbyte/32 Kword Bank D Bank C 8 x 8 Kbyte/4 Kword 32 Mbit + + Bank D 63 x 64 Kbyte/32 Kword
1
8 Mbit
Bank A
8 x 8 Kbyte/4 Kword + 15 x 64 Kbyte/32 Kword 16 x 8 Kbyte/4 Kword + 30 x 64 Kbyte/32 Kword
2
16 Mbit
Bank A + Bank D
3
24 Mbit
Bank B
48 x 64 Kbyte/32 Kword
4
32 Mbit
Bank A + Bank B
8 x 8 Kbyte/4 Kword + 63 x 64 Kbyte/32 Kword
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D. Simultaneous Operation Case 1 2 3 4 5 6 7 Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode* Bank 2 Status Read mode Autoselect mode Program mode Erase mode* Read mode Read mode Read mode
* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the Banks. 13
MBVD23381HJ-70
Sector Address Tables Sector Address Bank Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22
Address Range A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X
Bank Address A21 A20 A19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X
Word Mode
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh
Bank A
(Continued)
14
MB84VD23381HJ-70
Sector Address Bank Sector
SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
Address Range A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Bank Address A21 A20 A19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Word Mode
080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh
Bank B
(Continued)
15
MBVD23381HJ-70
Sector Address Bank Sector
SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
Address Range A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Bank Address A21 A20 A19
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Word Mode
200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh
Bank C
(Continued)
16
MB84VD23381HJ-70
(Continued)
Sector Address Bank Sector
SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
Address Range A14
X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
Bank Address A21 A20 A19
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
A13
X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1
Word Mode
380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3F8FFFh 3F9000h to 3F9FFFh 3FA000h to 3FAFFFh 3FB000h to 3FBFFFh 3FC000h to 3FCFFFh 3FD000h to 3FDFFFh 3FE000h to 3FEFFFh 3FF000h to 3FFFFFh
Bank D
17
MBVD23381HJ-70
Sector Group Addresses
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A15 0 0 0 0 0 0 0 0 1 0 1
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A14 0 0 0 0 1 1 1 1
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13 0 0 1 1 0 0 1 1
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12 0 1 0 1 0 1 0 1
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 to SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
0 0 1 1 1 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
18
MB84VD23381HJ-70
Flash Memory Autoselect Codes Type Manufacture's Code Device Code Extended Device Code *2 Sector Group Protection A21 to A12 BA BA BA BA Sector Group Addresses A6 L L L L L A3 L L H H L A2 L L H H L A1 L L H H H A0 L H L H L Code (HEX) 04h 227Eh 2202h 2201h 01h*1
Legend: L = VIL, H = VIH. See "s ELECTRICAL CHARACTERISTICS (DC Characteristics) " for voltage levels. *1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.
19
MBVD23381HJ-70
Flash Memory Command Definitions Command Sequence
Read/Reset Read/Reset Autoselect Program Program Suspend Program Resume Chip Erase Sector Erase Erase Suspend Erase Resume Extended Sector Group Protection *2 Set to Fast Mode Fast Program *1 Reset from Fast Mode *1 Query HiddenROM Entry HiddenROM Program *3 HiddenROM Exit *3 Bus Write Cycles Req'd
First Bus Write Cycle
Second Bus Write Cycle
Third Bus Write Cycle
Fourth Bus Read/Write Cycle -- RA -- PA -- -- 555h 555h -- -- SPA -- -- -- -- --
(HRA)
Fifth Bus Write Cycle
Sixth Bus Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXh 555h 555h 555h BA BA 555h 555h BA BA XXXh 555h XXXh BA (BA) 55h 555h 555h 555h F0h AAh AAh AAh B0h 30h AAh AAh B0h 30h 60h AAh A0h 90h 98h AAh AAh AAh -- 2AAh 2AAh 2AAh -- -- 2AAh 2AAh -- -- SPA 2AAh PA XXXh -- 2AAh 2AAh 2AAh -- 55h 55h 55h -- -- 55h 55h -- -- 60h 55h PD
*4
1 3 3 4 1 1 6 6 1 1 4 3 2 2 1 3 4 4
-- 555h (BA) 555h 555h -- -- 555h 555h -- -- SPA 555h -- -- -- 555h 555h
(HRBA)
-- F0h 90h A0h -- -- 80h 80h -- -- 40h 20h -- -- -- 88h A0h 90h
-- RD -- PD -- -- AAh AAh -- -- SD -- -- -- -- -- PD 00h
-- -- -- -- -- -- 2AAh 2AAh -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- 55h 55h -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- 555h SA -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- 10h 30h -- -- -- -- -- -- -- -- -- --
F0h -- 55h 55h 55h
PA XXXh
555h
*1: This command is valid during Fast Mode. *2: This command is valid while RESET = VID. *3: This command is valid during HiddenROM mode. *4: The data "00h" is also acceptable.
(Continued)
20
MB84VD23381HJ-70
(Continued)
Notes: * Address bits A21 to A11 = X = "H" or "L" for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA). * Bus operations are defined in "s DEVICE BUS OPERATIONS". * RA =Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A21, A20, A19) * RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. * SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. * HRA = Address of the HiddenROM area: 000000h to 00007Fh * HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL) * The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0 * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. * The command combinations not described in this table are illegal.
21
MBVD23381HJ-70
2. ELECTRICAL CHARACTERISTICS (AC Characteristics) * Read Only Operations Characteristics (Flash) Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- Standard tRC tACC tCEf tOE tDF tDF tOH tREADY Condition -- CEf = VIL OE = VIL OE = VIL -- -- -- -- -- Value (Note) Min 70 -- -- -- -- -- 0 -- Max -- 70 70 30 25 25 -- 20 Unit ns ns ns ns ns ns ns s
Note : Test Conditions- Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCCf Timing measurement reference level Input : 0.5 x VCCf Output : 0.5 x VCCf
22
MB84VD23381HJ-70
* Read Operation Timing Diagram (Flash)
tRC
Address
tACC
Address Stable
CEf
tOE tDF
OE
tOEH
WE
tCE High-Z tOH High-Z
Outputs
Outputs Valid
* Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
tACC
Address Stable
CEf
tRH
tRP
tRH
tCE
RESET
tOH High-Z
Outputs
Outputs Valid
23
MBVD23381HJ-70
* Write/Erase/Program Operations (Flash) Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling Symbol JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Standard tWC tAS tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tRB tRP tRH tBUSY tEOE tTOW tSPD Min 70 0 12 30 0 25 0 0 10 20 20 0 0 0 0 0 0 35 35 20 20 50 0 500 200 50 Value Typ 6 0.5 Max 90 70 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns ns ns ns s s
CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CEf Setup Time WE Setup Time CEf Hold Time WE Hold Time Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Programming Operation Sector Erase Operation * VCCf Setup Time Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time *: This does not include preprogramming time.
24
MB84VD23381HJ-70
* Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA tRC
Address
555h tWC
CEf
tCS tCH tCE
OE
tGHWL tWP tWPH tOE tWHWH1
WE
tDS tDH tDF tOH
Data
A0h
PD
DQ7
DOUT
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence.
25
MBVD23381HJ-70
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH PD DQ7 DOUT
Data
A0h
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence.
26
MB84VD23381HJ-70
* AC Waveforms Chip/Sector Erase Operations (Flash)
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS AAh tDH 55h 80h AAh 55h
30h for Sector Erase 10h/ 30h
Data
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
27
MBVD23381HJ-70
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCE * DQ7 = Valid Data
DQ7
Data
DQ7
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (the device has completed the Embedded operation).
28
MB84VD23381HJ-70
* AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO tAHT tAS
CEf
tCEPH
WE
tOEH
tOEPH tOEH
OE
tDH tOE tCE
DQ 6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
*
Stop
Toggling
Output Valid
RY/BY
* : DQ6 stops toggling (the device has completed the Embedded operation).
29
MBVD23381HJ-70
* Back-to-back Read/Write Timing Diagram (Flash)
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
Address
BA1
tAS
BA2 (555h)
tAH
BA1
tACC tCE
BA2 (PA)
BA1
tAS tAHT
BA2 (PA)
CEf
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF
DQ
Valid Output
Valid Input (A0h)
Valid Output
Valid Input (PD)
Valid Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2
30
MB84VD23381HJ-70
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
* RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
31
MBVD23381HJ-70
* Temporary Sector Unprotection (Flash)
VCCf
tVCS
tVIDR tVLHT
VID VIH RESET
CEf
WE
tVLHT Program or Erase Command Sequence tVLHT
RY/BY
Unprotection period
* Acceleration Mode Timing Diagram (Flash)
VCCf
tVCS
tVACCR tVLHT
VACC VIH WP/ACC
CEf
WE
tVLHT Program Command Sequence tVLHT
RY/BY
Acceleration period
32
MB84VD23381HJ-70
* Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVIDR
tVLHT tWC tWC SPAX SPAX SPAY
Address
A6, A3, A2, A0
A1
CEf
OE
tWP
TIME-OUT
WE Data
60h 60h 40h tOE 01h 60h
SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
33
MBVD23381HJ-70
3. ERASE AND PROGRAMMING PERFORMANCE (Flash) Parameter Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle Value Min -- -- -- 100,000 Typ 0.5 6 25.2 -- Max 2.0 100 95 -- Unit s s s cycle Data= Checker Remarks Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead
Typical Erase conditions TA = +25C, VCCf_1 & VCCf_2 = 2.9 V Typical Program conditions TA = +25C, VCCf_1 & VCCf_2 = 2.9 V
34
MB84VD23381HJ-70
s 16M FCRAM CHARACTERISTICS FOR MCP
1. AC Characteristics * READ OPERATION (16M FCRAM) Parameter Read Cycle Time Chip Enable Access Time Output Enable Access Time Address Access Time Output Data Hold Time CE1r Low to Output Low-Z OE Low to Output Low-Z CE1r High to Output High-Z OE High to Output High-Z Address Setup Time to CE1r Low Address Setup Time to OE Low LB / UB Setup Time to CE1r Low LB / UB Setup Time to OE Low Address Invalid Time Address Hold Time from CE1r Low Address Hold Time from OE Low Address Hold Time from CE1r High Address Hold Time from OE High LB / UB Hold Time from CE1r High LB / UB Hold Time from OE High CE1r Low to OE Low Delay Time OE Low to CE1r High Delay Time CE1r High Pulse Width OE High Pulse Width *1 *2 *3 Symbol tRC tCE tOE tAA tOH tCLZ tOLZ tCHZ tOHZ tASC tASO tASO[ABS] tBSC tBSO tAX tCLAH tOLAH tCHAH tOHAH tCHBH tOHBH tCLOL tOLCH tCP tOP tOP[ABS] Value Min 80 -- -- -- 5 5 0 -- -- -5 25 5 -5 0 -- 80 45 -5 -5 -5 -5 25 45 10 25 10 Max -- 60 35 60 -- -- -- 20 20 -- -- -- -- -- 5 -- -- -- -- -- -- 1000 -- -- 1000 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes
*1, *3 *1 *1, *4 *1 *2 *2 *2 *2 *5 *3, *6 *7 *5 *4, *8 *4 *4, *9
*3, *6, *9, *10 *9 *6, *9, *10 *7
: The output load is 30 pF with 1 TTL. : The output load is 5 pF. : The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4 : Applicable only to A0, A1 and A2 when both CE1r and OE are kept at Low for the address access. *5 : Applicable if OE is brought to Low before CE1r goes Low. *6 : The tASO, tCLOL(Min) and tOP(Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(Min), during OE control access (ie., CE1r stays Low), the tOE become tOE(Max) + tASO(Min) - tASO(actual). *7 : The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *8 : The tAX is applicable when all or two addresses among A0 to A2 are switched from previous state. *9 : If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC(Min) - tCLOL(actual) or tRC(Min) - tOP(actual). *10 : Maximum value is applicable if CE1r is kept at Low. 35
MBVD23381HJ-70
* WRITE OPERATION (16M FCRAM) Parameter Write Cycle Time Address Setup Time Address Hold Time CE1r Write Setup Time CE1r Write Hold Time WE Setup Time WE Hold Time LB and UB Setup Time LB and UB Hold Time OE Setup Time OE Hold Time OE High to CE1r Low Setup Time OE High to Address Hold Time CE1r Write Pulse Width WE Write Pulse Width CE1r Write Recovery Time WE Write Recovery Time Data Setup Time Data Hold Time CE1r High Pulse Width *1 *2 *3 Symbol tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH[ABS] tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCP Value Min 80 0 35 0 0 0 0 -5 -5 0 25 12 -5 -5 45 45 20 20 15 0 10 Max -- -- -- 1000 1000 -- -- -- -- 1000 1000 -- -- -- -- -- -- 1000 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *10 *3 *3, *4 *5 *6 *7 *1, *8 *1, *8, *9 *1, *10 *1, *3, *10 Notes *1 *2, *9 *2 *9
: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR). : New write address is valid from either CE1r or WE is bought to High. : The tOEH is specified from end of tWC(Min). The tOEH(Min) is a reference value when the access time is determined by tOE. If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. : The tOEH(Max) is applicable if CE1r is kept at Low and both WE and OE are kept at High. : The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stays Low. : tOHCL(Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL(Min), WE Low must be asserted after tRC(Min) from CE1r Low. In other words, read operation is initiated if tOHCL(Min) is not satisfied. : Applicable if CE1r stays Low after read operation. : tCW and tWP is applicable if write operation is initiated by CE1r and WE, respectively. , : If write operation is terminated by WE followed by CE1r = H, the sum of actual tCS and tWP and the sum of actual tAS and tWP must be equal or greater than 60 ns. For example, if actual tWP is 45 ns, tCS and tAS must be equal or greater than 15 ns.
*4 *5 *6
*7 *8 *9
*10 : tWRC and tWR is applicable if write operation is terminated by CE1r and WE, respectively. In case CE1r is brought to High before satisfaction of tWR(Min), the tWRC(Min) is also applied. 36
MB84VD23381HJ-70
* POWER DOWN PARAMETERS (16M FCRAM) Value Parameter CE2r Low Setup Time for Power Down Entry CE2r Low Hold Time after Power Down Entry CE1r High Hold Time following CE2r High after Power Down Exit CE1r High Setup Time following CE2r High after Power Down Exit * OTHER TIMING PARAMETERS (16M FCRAM) Value Parameter CE1r High to OE Invalid Time for Standby Entry CE1r High to WE Invalid Time for Standby Entry CE2r Low Hold Time after Power-up CE2r High Hold Time after Power-up CE1r High Hold Time following CE2r High after Power-up CE1r and CE2r High Hold Time during Power-up Input Transition Time Symbol Min tCHOX tCHWX tC2LH tC2HL tCHH tCHHP tT 10 10 50 50 350 400 1 Max -- -- -- -- -- -- 25 ns ns s s s s ns *4 *1 *2 *3 *2 Unit Note Symbol Min tCSP tC2LP tCHH tCHS 10 80 350 10 Max -- -- -- -- ns ns s ns Unit Note
*1 : Some data might be written into any address location if tCHWX(Min) is not satisfied. *2 : Must satisfy tCHH(Min) after tC2LH(Min). *3 : Requires Power Down mode entry and exit after tC2HL. *4 : The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, each AC specification must be relaxed accordingly.
* AC TEST CONDITIONS (16M FCRAM) Symbol VIH VIL VREF tT Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Test Setup -- -- -- Between VIL and VIH Value VCCr 0.0 0.5 x VCCr 5 Unit V V V ns Note
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MBVD23381HJ-70
* READ Timing #1 (OE Control Access) (16M FCRAM)
tRC
tRC
ADDRESS
ADDRESS VALID
tCE tOHAH tASO
ADDRESS VALID
tOHAH
CE1r
tOLCH tCLOL tOE tOP tOE
OE
tASO tBSO tOHBH tBSO tOHBH
LB, UB
tOHZ tOLZ tOH tOLZ tOHZ tOH
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note : CE2r and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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MB84VD23381HJ-70
* READ Timing #2 (CE1r Control Access) (16M FCRAM)
tRC
tRC ADDRESS VALID tCHAH tASC tCE tCHAH
ADDRESS
tASC
ADDRESS VALID tCE
CE1r
tCP
OE
tBSC tCHBH tBSC tCHBH
LB, UB
tCHZ tCLZ tOH tCLZ tCHZ tOH
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note : CE2r and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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MBVD23381HJ-70
* READ Timing #3 (Address Access after OE Control Access) (16M FCRAM)
tRC tRC ADDRESS VALID (No change)
ADDRESS (A19 to A3) ADDRESS (A2 to A0) CE1r
ADDRESS VALID
ADDRESS VALID tASO tOLAH tAX
ADDRESS VALID tAA tOHAH
tOE
tOHZ
OE
tBSO tOHBH
LB, UB
tOLZ tOH tOH
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note : CE2r and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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MB84VD23381HJ-70
* READ Timing #4 (Address Access after CE1r Control Access) (16M FCRAM)
tRC
tRC ADDRESS VALID (No change)
ADDRESS (A19 to A3) ADDRESS (A2 to A0)
tASC
ADDRESS VALID
ADDRESS VALID tCLAH tAX
ADDRESS VALID tAA tCHAH
CE1r
tCE tCHZ
OE
tBSC tCHBH
LB, UB
tCLZ tOH tOH
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note : CE2r and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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MBVD23381HJ-70
* WRITE Timing #1 (CE1r Control) (16M FCRAM)
tWC
ADDRESS
tAS
ADDRESS VALID tAH tAS
CE1r
tCW tWS tWH tWRC tWS
WE
tBS tBH tBS
UB, LB
tOHCL
OE
tDS tDH
DQ (Input)
VALID DATA INPUT
Note : CE2r must be High for write cycle.
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MB84VD23381HJ-70
* WRITE Timing #2-1 (WE Control, Single Write Operation) (16M FCRAM)
tWC
ADDRESS
tOHAH tAS
ADDRESS VALID tAH tCH tAS
CE1r
tOHCL tCS tWP tWR
tWRC/tCP
WE
tBH tBS tBH
UB, LB
tOES
OE
tOHZ tDS tDH
DQ (Input)
VALID DATA INPUT
Note : CE2r must be High for write cycle.
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MBVD23381HJ-70
* WRITE Timing #2-2 (WE Control, Continuous Write Operation) (16M FCRAM)
tWC
ADDRESS
tOHAH tAS
ADDRESS VALID tAH tAS
CE1r
tOHCL tCS tWP tWR
WE
tOHBH tBS tBH tBS
UB, LB
tOES
OE
tOHZ tDS tDH
DQ (Input)
VALID DATA INPUT
Note : CE2r must be High for write cycle.
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MB84VD23381HJ-70
* READ / WRITE Timing #1-1 (CE1r Control) (16M FCRAM)
tWC
ADDRESS
tCHAH tAS
WRITE ADDRESS tAH tASC
READ ADDRESS
CE1r
tCP tWH tWS tCW tWH tWRC tWS tCLOL
WE
tCHBH tBS tBH tBSO
UB, LB
tOHCL
OE
tCHZ tOH tDS tDH tOLZ
DQ
READ DATA OUTPUT WRITE DATA INPUT
Note : Write address is valid from either CE1r or WE of last falling edge.
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MBVD23381HJ-70
* READ / WRITE Timing #1-2 (CE1r Control) (16M FCRAM)
tRC
ADDRESS
tASC tWRC
READ ADDRESS tCHAH tAS
WRITE ADDRESS
CE1r
tWRC(Min) tWH tWS tCE tWH
tCP tWS
WE
tBH tBSC tCHBH tBS
UB, LB
tOEH tOHCL
OE
tCHZ tDH tCLZ tOH
DQ
WRITE DATA INPUT READ DATA OUTPUT
Note : The tOEH is specified from the time satisfied both tWRC and tWR(Min).
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MB84VD23381HJ-70
* READ (OE Control) / WRITE (WE Control) Timing #2-1 (16M FCRAM)
tWC
ADDRESS
tOHAH tAS
WRITE ADDRESS tAH
READ ADDRESS tASO
CE1r
Low tWP tWR tOEH
WE
tOHBH tBS tBH tBSO
UB, LB
tOES
OE
tOHZ tOH tDS tDH tOLZ
DQ
READ DATA OUTPUT WRITE DATA INPUT
Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE.
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MBVD23381HJ-70
* READ (OE Control) / WRITE (WE Control) Timing #2-2 (16M FCRAM)
tRC
ADDRESS
tASO
READ ADDRESS VALID tOHAH
WRITE ADDRESS tAS
CE1r
Low tWR tOEH
WE
tBH tBSO tOHBH tBS
UB, LB
tOE tOES
OE
tDH tOLZ tOHZ tOH
DQ
WRITE DATA INPUT READ DATA OUTPUT
Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE.
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MB84VD23381HJ-70
* Standby Entry Timing after Read or Write (16M FCRAM)
CE1r
tCHOX tCHWX
OE
WE
Active (Read) Standby Active (Write) Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(Min) period from either last address transition of A0, A1 and A2, or CE1r Low to High transition.
* POWER DOWN Entry and Exit Timing (16M FCRAM)
CE1r
tCHS
CE2r
tCSP tC2LP High-Z tCHH
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note : This Power Down mode can be also used for Power-up #2 below.
49
MBVD23381HJ-70
* POWER-UP Timing #1 (16M FCRAM)
CE1r
tCHS tC2LH tCHH
CE2r
VCCr
0V
VCCr Min
Note : The tC2LH specifies after VCCr reaches specified minimum level. * POWER-UP Timing #2 (16M FCRAM)
CE1r
tCHS tC2HL tCSP tC2LP tCHH
CE2r
tC2HL
VCCr
0V
VCCr Min
Note : The tC2HL specifies from CE2r Low to High transition after VCCr reaches specified minimum level. CE1r must be brought to High prior to or together with CE2r Low to High transition. * POWER-UP Timing #3 (16M FCRAM)
CE1r
tCHHP
CE2r
VCCr
0V
VCCr Min
Note : Both CE1r and CE2r must be High together with VCCr. Otherwise either POWER-UP Timing #1 or #2 must be used for proper operation. 50
MB84VD23381HJ-70
2. DATA RETENTION * Low VCCr Characteristics (16M FCRAM) Parameter VCCr Data Retention Supply Voltage Symbol VDRs Test Conditions CE1r = CE2r VCCr - 0.2 V or CE1r = CE2r = VIH, VCCr = VCCr Max, VIN 0.2 V or VIN VCCr - 0.2V, CE1r = CE2r VCCr - 0.2 V, IOUT = 0 mA VCCr = VCCr at data retention entry VCCr = VCCr after data retention -- Min 2.3 Max 3.1 Unit V
VCCr Data Retention Supply Current
IDR1s
--
70
s
Data Retention Setup Time Data Retention Recovery Time VCCr Voltage Transition Time
tDRSs tDRRs V/t
0 100 0.2
-- -- --
ns ns V/s
* Data Retention Timing (16M FCRAM)
tDRS 3.1 V VCCr 2.7 V CE2r 2.3 V CE1r VIH > VCCr - 0.2 V V/t V/t tDRR
0.4 V VSS Data Retention Mode Data bus must be in High-Z at data retention entry.
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MBVD23381HJ-70
s PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Condition VIN = 0 VOUT = 0 VIN = 0 Value Min Typ Max 20.0 25.0 25.0 Unit pF pF pF
Note : Test conditions TA = +25C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
s CAUTION
* The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET. * Without the high voltage (VID) , sector group protection can be achieved by using "Extended Sector Group Protection" command at Table "Flash Memory Commmand Definitions" in "s 64M FLASH MEMORY CHARACTERISTICS FOR MCP".
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MB84VD23381HJ-70
s ORDERING INFORMATION
MB84VD23381 HJ -70 PBS
PACKAGE TYPE PBS = 56-ball BGA SPEED OPTION
Device Revision
DEVICE NUMBER/DESCRIPTION 64M-bit (4M x 16-bit) Dual Operation Flash Memory 3.0V-only Read, Program, and Erase 16M-bit (1M x 16-bit) Mobile FCRAM
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MBVD23381HJ-70
s PACKAGE DIMENSION
56-ball plastic FBGA (BGA-56P-M04)
9.000.10(.354.004) 1.09 .043
+0.11 -0.10 +.004 -.004
0.20(.008) S B
(Seated height)
B 0.40(.016) REF 0.80(.031) REF 8 7 6 5 4 3 2 1 HGFEDCBA INDEX MARK
0.390.10 (Stand off) (.015.004) 0.80(.031) REF A 7.000.10 (.276.004)
0.40(.016) REF 0.10(.004) S S
INDEX-MARK AREA
0.20(.008) S A 56-o0.45 +0.10 -0.05 56-o.018 +.004 -.002
o0.08(.003)
M
S AB
0.10(.004) S
C
2003 FUJITSU LIMITED B56004S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
54
MB84VD23381HJ-70
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0402 (c) FUJITSU LIMITED Printed in Japan

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